Prior art potentiometric digital-to-analog converters (DAC) utilize two cascaded resistor divider strings, as shown in FIG. 1. A course resistor divider is connected between ground and a reference voltage and provides 2.sup.M equal resistor segments where M represents the number of course divider bits used to select where to tap a voltage along the course resistor divider. A fine resistor divider is connected through a set of coarse divider switches across one of the coarse divider segments selected by the M coarse divider bits. The fine resistor divider has equally valued segments and subdivides the resistance of the selected coarse divider segment to provide an analog voltage output. Typically, the fine resistor divider is controlled by N fine divider bits, and the resolution of the DAC is M+N bits.
A major problem with the prior art DAC is a linearity error caused by the switches which couple the fine and coarse resistor dividers. Typically, the coupling switches are NMOS transistors, as are known in the art, which carry current which produces a voltage drop across the switch introducing the linearity error. As the error approaches the voltage step defined by the least significant bit (LSB), the DAC will produce an incorrect voltage output. The prior art proposes to mitigate the linearity error of the switches by using a fine divider which consists of only 2.sup.N -1 resistors and attempting to match the on-resistance of the coupling switches to a fraction of the resistance of a fine divider segment. In this way, the error introduced by the coupling switches should be less than the resolution defined by a fine resistor divider segment. However, the attempt to match resistance is extremely poor due to process and temperature variations. Therefore, differential non-linearity degrades significantly in the prior art DAC.
Another major problem with the prior art DAC is that the attempts to match the resistances of the coupling switch and divider segment require the reference voltage to be less than half of the supply voltage. Generally, this requires the addition of an amplifier to approximately double the output voltage to restore its voltage range. However, as a result, the integral linearity and noise immunity performance of the prior art DAC is degraded by about one-half.
There is a need for a precision high-resolution DAC that has a linearity better than a resolution of 1/2 LSB. There is also a need for a DAC that can utilize approximately the full rail-to-rail voltage of the voltage source without the use of additional amplifiers. In addition, it would be an advantage to provide a DAC with a minimal number of switches so as to reduce size and cost. Another improvement, would be to provide a DAC utilizing all CMOS devices and including NMOS and PMOS switches while minimizing the linearity error contribution by the on-resistance of the switches.